Memory devices typically are composed of an array of bit cells, with each bit cell storing a corresponding bit of data. Each bit cell generally is configured as one or more transistors that store or retain an electrical charge or voltage representative of a bit value (e.g., a logic “0” or a logic “1”). In “register file”-type memory devices, each bit cell has a write input (composed of a write word line and one or more write bit lines) and a separate read input (composed of a read word line and one or more read bit lines) that can be independently accessed. In these types of memory devices, the robustness of a write access typically is determined based on the voltage levels of the bit cell storage nodes after the write word line input to the bit cell is deasserted. A write access typically is considered to be robust when there is rail-to-rail separation between the storage nodes; that is, one node is substantially close to the high voltage level (for example, VDD), while the other node is substantially close to the low voltage level (for example, GND), thereby indicating stabilization of the voltage levels at the storage nodes. In operations whereby a write access to a bit cell is immediately followed by a read access to the same bit cell, such as during a write-verify access, if the storage nodes of a bit cell are not sufficiently stable by the deassertion of the write word line or the following assertion of the read word line, an incorrect bit value may be improperly sensed during the read access, thereby causing a functional failure for the memory device.
In many implementations, “register file”-type memory devices are configured such that write accesses occur during one phase of the clock cycle, while read accesses occur during the other phase of the clock cycle. In view of this arrangement, one conventional technique for reducing the likelihood of an erroneous read access following a write access to a bit cell includes slowing the clock signal so as to allow more time for the bit cell to stabilize during a write access before it is subjected to a following read access. However, slowing the clock results in a decrease in the number of possible accesses per unit time, thereby negatively affecting the performance of the memory device. Accordingly, an improved technique for performing write accesses to a memory device would be advantageous.
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